JTAG/Boundary Scan is probably the most ingenious test process, which like ICT, tests within the circuit and detects structural fault locations by setting thousands of test points, even under BGAs, - with only four test bus lines.
Boundary Scan essentially means “testing at the periphery (boundaries) of a circuit”.
In addition to the core logic and the test points, an IC (Integrated Circuit) also features some test control logic. The test points are integrated between the core logic and the physical pins of the IC. This special IC architecture and the test bus connections among each chip are preconditions for the use of Boundary Scan. If they are met it is possible
- test particular components
- test the connections among the ICs on the board
- test the function of complete boards under operating conditions
Not all components on the board have to be testable in order to use the Boundary Scan philosophy. Even if only one component meets the requirement, Boundary Scan can be used for certain test applications. Please ask us to run a testability analysis on your boards to show that there are thousands of components that can be tested with Boundary Scan.
Unlike other test access methodologies, Boundary Scan can be utilised from the beginning to the end of the production of a PCB for the following applications:
- design verification
- in-system programming